Ukeiley, Richard Larry
Person
Found in 9 Collections and/or Records:
ADSL line card design, 2000
Item — Call number MU Thesis Zha
Identifier: b2194994
Abstract
The document discusses an ADSL (Asymmetric Digital Subscriber Line) line card project for broadband access. ADSL line card is a module installed at ATU-C side (ADSL Transmission Unit, Central), which provides ADSL line interface and PHY (Physical layer) mulitplex function. The document also describes the functional blocks on this card and focuses on the design of two sections: the control FPGA (Field-programmable gate array) and the LVDS (Low Voltage Differential Signaling) serial...
Dates:
2000
Found in:
Monmouth University Library Archives
CPU design and modeling using Verilog HDL, 1997
Item — Call number MU Thesis Kan
Identifier: b2088066
Abstract
Integrated Circuit design with Hardware Description Languages improves productivity and provides flexibility. A new CPU is designed with its own instruction set. Verilog HDL is used to build a behavioral model of the CPU. Validation of the model is performed using simulation. The CPU is synthesized for a Xilinx FPGA and the netlist generated in the Xilinx format.
Dates:
1997
Found in:
Monmouth University Library Archives
Design and simulation of a pipelined arithmetic and logic unit, 2002
Item — Call number MU Thesis Gok
Identifier: b2089047
Abstract
Modern microprocessors are designed to execute arithmetic and logical instructions in one clock time. Emerging microprocessors implement multimedia instructions as part of the Instruction Set Architecture (ISA) and expect to run them in a single clock cycle. Designing circuits to implement multi-media instructions that execute in a single clock cycle poses a serious challenge to microprocessor designers. Sustained performance of the Arithmetic and Logic Unit (ALU) is very critical to the...
Dates:
2002
Found in:
Monmouth University Library Archives
Developing a PC-based infrared voice-activated television remote controller, 2000
Item — Call number MU Thesis Van
Identifier: b2087784
Abstract
This paper presents the results of a graduate research project that is required in partial fulfillment for obtaining a Master of Electronic Engineering degree from Monmouth University. The objective of this project was to investigate the infrared (IR) signal characteristics for a television remote control and to analyze techniques for developing an IR interface between a personal computer (PC) and television. The paper describes an approach and the challenges associated with creating this...
Dates:
2000
Found in:
Monmouth University Library Archives
Direct digital synthesizer, 1997
Item — Call number MU Thesis Gon
Identifier: b2088057
Abstract
This report describes the theory and implementation of a direct digital frequency synthesizer (DDS). This synthesizer will be used as a high resolution signal generator with an output frequency range of 25 Hz to 100 kHz, in 25 Hz steps. The report will provide a description of the realization of the DDS control system which enables the frequency synthesis, using a computer hardware description language to configure and implement the entire control system within a single programmable logic...
Dates:
1997
Found in:
Monmouth University Library Archives
Field Programmable Gate Arrays and their applications to digital signal processing, 1998
Item — Call number MU Thesis Bal
Identifier: b2194801
Abstract
Application such as data communications and signal processing require extensive processing power, but when the DSP processing power is not sufficient, the only alternatives have been to add multiple DSP processors or use custom gate arrays. Multiple processor solutions are expensive, require many components, consume too much power and the solution does not always provide the performance needed to differentiate products. Custom gate array solutions deliver the performance but sacrifice...
Dates:
1998
Found in:
Monmouth University Library Archives
Hardware design tool based on Xilinx State Machine method, 1998
Item — Call number MU Thesis Rod
Identifier: b2089700
Abstract
This paper describes the Xilinx State Machine design methodology consisting of one flip-flop per state and only one state bit active at any time. This method is used for the design of a tool that will allow a designer to run a simulation and generate hardware of a state machine. The systematic approach of this design method facilitates the construction of such tool. This paper discusses the data required to represent the state machine and how it operates on the internal data structure to...
Dates:
1998
Found in:
Monmouth University Library Archives
The design of a VHDL BCH (15,7) encoder and decoder, 1999
Item — Call number MU Thesis Pel
Identifier: b2087782
Abstract
Bose-Chadhuri-Hocquenghem (BCH) codes belong to a powerful class of cyclic block codes that can be used to improve the performance of a communication link by detecting or correcting errors. BCH codes are considered to be the best of the binary block codes and are commonly used as a Forward Error Correction (FEC) technique in military and commercial communcation systems. Since the discovery of BCH codes, many mathematicians have developed decoding algorithms that can be implemented in...
Dates:
1999
Found in:
Monmouth University Library Archives
Using field programmable gate arrays in digital signal processing application, 2000
Item — Call number MU Thesis Yan
Identifier: b2194830
Abstract
Todays, [sic] expanded demand for digital signal processors (DSPs) require them to perform at higher and higher data rates. Many of the existing commercial available general purpose DSPs with their generic mulitply and add structure do not adequately meet this high data rate signal processing requirement. However, recent advances in higher density and faster field programmable gate arrays (FPGAs) have shown that, as configurable digital signal processing...
Dates:
2000
Found in:
Monmouth University Library Archives