Modern microprocessors are designed to execute arithmetic and logical instructions in one clock time. Emerging microprocessors implement multimedia instructions as part of the Instruction Set Architecture (ISA) and expect to run them in a single clock cycle. Designing circuits to implement multi-media instructions that execute in a single clock cycle poses a serious challenge to microprocessor designers. Sustained performance of the Arithmetic and Logic Unit (ALU) is very critical to the design of such instructions. Typically, elaborate modules such as high-speed adders and multipliers are used while designing such units resulting in increased silicon real-estate, cost and power requirements. We propose a novel approach to make the ALU, a pipelined unit (P-ALU) in its own right leading to 4x performance for the cost of 1x real-state. This will result in faster clock speeds of P-ALU independent of the core clock (typically 4x of CPU clock). We believe that the core CPU can dispatch multiple instructions to several such autonomous pipelined-ALU units concurrently, resulting in very high performancee.

In this project, we have designed, implemented and simulated a simple pipelined arithmetic and logical unit (PALU) simulation using Verilog Hardware Description language. Our results show a 4x-time improvement in execution of ALU instructions.