The design of a VHDL BCH (15,7) encoder and decoder, 1999

Item — Call Number: MU Thesis Pel

Identifier: b2087782

Staff Only

Scope and Contents

From the Collection:

The collection consists of theses written by students enrolled in the Monmouth University graduate Electrical Engineering program. The holdings are bound print documents that were submitted in partial fulfillment of requirements for the Master of Science degree.

Dates

Creation: 1999

Creator

Pelishek, Michael R. (Author, Person)
Ukeiley, Richard Larry (Thesis advisor, Person)

Conditions Governing Access

The collection is open for research use. Access is by appointment only.

Access to the collection is confined to the Monmouth University Library and is subject to patron policies approved by the Monmouth University Library.

Collection holdings may not be borrowed through interlibrary loan.

Research appointments are scheduled by the Monmouth University Library Archives Collections Manager (723-923-4526). A minimum of three days advance notice is required to arrange a research appointment for access to the collection.

Patrons must complete a Researcher Registration Form and provide appropriate identification to gain access to the collection holdings. Copies of these documents will be kept on file at the Monmouth University Library.

Extent

1 Items (print book) : 97 pages ; 8.5 x 11.0 inches (28 cm).

Language of Materials

English

Additional Description

Abstract

Bose-Chadhuri-Hocquenghem (BCH) codes belong to a powerful class of cyclic block codes that can be used to improve the performance of a communication link by detecting or correcting errors. BCH codes are considered to be the best of the binary block codes and are commonly used as a Forward Error Correction (FEC) technique in military and commercial communcation systems. Since the discovery of BCH codes, many mathematicians have developed decoding algorithms that can be implemented in hardware. This project documents the design and implementaton of a VHSIC Hardware Description Language (VHDL) encoder and decoder for BCH (15,7) capable of correcting all single errors and all double errors. In the course of this work, an error trapping Meggitt BCH decoder using shift register sequences was modified and the resulting modified decoder algorithm is capable of correcting up to two errors operating at line speed.

Partial Contents

1. Introduction -- 2. Encoder algorithm -- 3. Decoder algorithm -- 4. Encoder design details -- 5. Decoder design details -- 6. Conclusion -- Appendix A. Encoder VHDL source code -- Appendix B. BCH decoder VHDL source code -- Appendix C. Simulator source code for encoder and decoder -- Appendix D. MATLAB .m files for encoder and decoder -- Appendix E. Schematic diagrams for encoder and decoder -- Appendix F. Simulator output -- List of references.