ADSL line card design, 2000

Item — Call Number: MU Thesis Zha

Identifier: b2194994

Staff Only

Scope and Contents

From the Collection:

The collection consists of theses written by students enrolled in the Monmouth University graduate Electrical Engineering program. The holdings are bound print documents that were submitted in partial fulfillment of requirements for the Master of Science degree.

Dates

Creation: 2000

Creator

Zhang, Rong (Author, Person)
Ukeiley, Richard Larry (Thesis advisor, Person)

Conditions Governing Access

The collection is open for research use. Access is by appointment only.

Access to the collection is confined to the Monmouth University Library and is subject to patron policies approved by the Monmouth University Library.

Collection holdings may not be borrowed through interlibrary loan.

Research appointments are scheduled by the Monmouth University Library Archives Collections Manager (723-923-4526). A minimum of three days advance notice is required to arrange a research appointment for access to the collection.

Patrons must complete a Researcher Registration Form and provide appropriate identification to gain access to the collection holdings. Copies of these documents will be kept on file at the Monmouth University Library.

Extent

1 Items (print book) : 60 pages ; 8.5 x 11.0 inches (28 cm).

Language of Materials

English

Additional Description

Abstract

The document discusses an ADSL (Asymmetric Digital Subscriber Line) line card project for broadband access. ADSL line card is a module installed at ATU-C side (ADSL Transmission Unit, Central), which provides ADSL line interface and PHY (Physical layer) mulitplex function. The document also describes the functional blocks on this card and focuses on the design of two sections: the control FPGA (Field-programmable gate array) and the LVDS (Low Voltage Differential Signaling) serial interface to the ATM (Asynchronous Transfer Mode) switch.

Partial Contents

1. Introduction -- 2. System application -- 3. FPGA -- 4. LVDS bus -- 5. Conclusion -- Appendix A. FPGA schematic -- Appendix B. LVDS transceiver datasheet -- Appendix C. How to evaluate the LVDS bus interface with LineSim