Using field programmable gate arrays in digital signal processing application, 2000

Item — Call Number: MU Thesis Yan

Identifier: b2194830

Staff Only

Scope and Contents

From the Collection:

The collection consists of theses written by students enrolled in the Monmouth College and Monmouth University graduate Electronic Engineering programs. The holdings are bound print documents that were submitted in partial fulfillment of requirements for the Master of Science degree.

Dates

Creation: 2000

Creator

Yang, Qiu-Ting (Author, Person)
Ukeiley, Richard Larry (Thesis advisor, Person)

Conditions Governing Access

All analog collection holdings are limited to library use only.

Researchers seeking to photocopy collection materials must complete an Application to Photocopy Form.

In some cases, photocopying of collection materials may be performed by the Monmouth University Library staff.

The Monmouth University Library reserves the right to limit or refuse duplication requests subject to the condition of collection materials and/or restrictions imposed by the collection creators or by the United States Copyright Act.

Permission to examine, or copy, collection materials does not imply permission to publish or quote. It is the responsibility of the researcher to obtain such permissions from both the copyright holder and Monmouth University.

Extent

1 Items (print book) : 73 pages ; 8.5 x 11.0 inches (28 cm).

Language of Materials

English

Additional Description

Abstract

Todays, [sic] expanded demand for digital signal processors (DSPs) require them to perform at higher and higher data rates. Many of the existing commercial available general purpose DSPs with their generic mulitply and add structure do not adequately meet this high data rate signal processing requirement. However, recent advances in higher density and faster field programmable gate arrays (FPGAs) have shown that, as configurable digital signal processing engines, they provide reprogrammable features for DSP designs that can be operated at significantly higher speed for many digital signal processing applications.

The Finite Impulse Responses (FIR) filter and the Infinite Impulse Response (IIR) filter are two of the most commonly used functions in digital signal processsing. The main processing engine of the digital filter algorithm is the Multiply and Accumulate (MAC) function. FPGAs have an advantage of having parallel structures, which gives them the ability to implement MACs efficiently. As several generations of FPGAs have developed, they have reached the performance and cost goals, which allows a much wider spectrum of application support. In addition, a Hardware Description Language (HDL) methodology has been developed to help engineers design ever larger and more complex FPGA applications while meeting their tight time-to-market requirements.

The main focus of this project was to design two digital filters, a 16-Tap FIR filter and an 8th order IIR filter. MATLAB was the selected tool used to generate the filter coefficients and VHDL was used to design, synthesize, implement, and test the filter in a FPGA. A Serial Distributed Arithmetic (SDA) technique was used for the FPGAs implementation of the 16-Tap FIR filter, and the cascading of four identical 2nd order filters was used to illustrate the 8th order IIR filter.

The project report is arranged such that section 1 explained how FPGA DSP implementations have become an integral part of many high speed digital signal processing applications. Sections 2 and 3 provided an overview of FPGAs and VHDL, while section 4 described the design flow and software tools used in this project. Finally, the fifth section states the conclusions. Appendices A and B contained the VHDL test codes and VHDL reference table.

Partial Contents

1. Introduction -- 2. FPGAs overview -- 3. Hardware Description Language -- 4. FPGA-based filter applications -- 5. Conclusion -- 6. Reference -- Appendix A. VHDL codes for input signals -- 7. Appendix B. VHDL reference table.