CPU design and modeling using Verilog HDL, 1997

Item — Call Number: MU Thesis Kan

Identifier: b2088066

Staff Only

Scope and Contents

From the Collection:

The collection consists of theses written by students enrolled in the Monmouth College and Monmouth University graduate Electronic Engineering programs. The holdings are bound print documents that were submitted in partial fulfillment of requirements for the Master of Science degree.

Dates

Creation: 1997

Creator

Kandappan, Sumathi (Author, Person)
Ukeiley, Richard Larry (Thesis advisor, Person)

Conditions Governing Access

All analog collection holdings are limited to library use only.

Researchers seeking to photocopy collection materials must complete an Application to Photocopy Form.

In some cases, photocopying of collection materials may be performed by the Monmouth University Library staff.

The Monmouth University Library reserves the right to limit or refuse duplication requests subject to the condition of collection materials and/or restrictions imposed by the collection creators or by the United States Copyright Act.

Permission to examine, or copy, collection materials does not imply permission to publish or quote. It is the responsibility of the researcher to obtain such permissions from both the copyright holder and Monmouth University.

Extent

1 Items (print book) : 35 pages ; 8.5 x 11.0 inches (28 cm).

Language of Materials

English

Additional Description

Abstract

Integrated Circuit design with Hardware Description Languages improves productivity and provides flexibility. A new CPU is designed with its own instruction set. Verilog HDL is used to build a behavioral model of the CPU. Validation of the model is performed using simulation. The CPU is synthesized for a Xilinx FPGA and the netlist generated in the Xilinx format.

Partial Contents

1. Introduction -- 2. Hardware description languages -- 3. Logic design process -- 4. Verilog Hardware Description Language -- 5. Verilog simulation -- 6. Verilog synthesis -- 7. CPU architecture -- 8. CPU implementation -- 9. Conclusion -- Appendices -- Bibliography.