Abstract The document discusses an ADSL (Asymmetric Digital Subscriber Line) line card project for broadband access. ADSL line card is a module installed at ATU-C side (ADSL Transmission Unit, Central), which provides ADSL line interface and PHY (Physical layer) mulitplex function. The document also describes the functional blocks on this card and focuses on the design of two sections: the control FPGA (Field-programmable gate array) and the LVDS (Low Voltage Differential Signaling) serial...

Abstract

Integrated Circuit design with Hardware Description Languages improves productivity and provides flexibility. A new CPU is designed with its own instruction set. Verilog HDL is used to build a behavioral model of the CPU. Validation of the model is performed using simulation. The CPU is synthesized for a Xilinx FPGA and the netlist generated in the Xilinx format.

Abstract Modern microprocessors are designed to execute arithmetic and logical instructions in one clock time. Emerging microprocessors implement multimedia instructions as part of the Instruction Set Architecture (ISA) and expect to run them in a single clock cycle. Designing circuits to implement multi-media instructions that execute in a single clock cycle poses a serious challenge to microprocessor designers. Sustained performance of the Arithmetic and Logic Unit (ALU) is very critical to the...

Abstract Bose-Chadhuri-Hocquenghem (BCH) codes belong to a powerful class of cyclic block codes that can be used to improve the performance of a communication link by detecting or correcting errors. BCH codes are considered to be the best of the binary block codes and are commonly used as a Forward Error Correction (FEC) technique in military and commercial communcation systems. Since the discovery of BCH codes, many mathematicians have developed decoding algorithms that can be implemented in...

Abstract Todays, [sic] expanded demand for digital signal processors (DSPs) require them to perform at higher and higher data rates. Many of the existing commercial available general purpose DSPs with their generic mulitply and add structure do not adequately meet this high data rate signal processing requirement. However, recent advances in higher density and faster field programmable gate arrays (FPGAs) have shown that, as configurable digital signal processing...