Call number MU Thesis Kan
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CPU design and modeling using Verilog HDL, 1997
Item — Call Number: MU Thesis Kan
Identifier: b2088066
Abstract
Integrated Circuit design with Hardware Description Languages improves productivity and provides flexibility. A new CPU is designed with its own instruction set. Verilog HDL is used to build a behavioral model of the CPU. Validation of the model is performed using simulation. The CPU is synthesized for a Xilinx FPGA and the netlist generated in the Xilinx format.
Dates:
1997