Error detection and correction in digital data communication, 1972

Item — Multiple Containers

Identifier: b2088519

Staff Only

Scope and Contents

From the Collection:

The collection consists of theses written by students enrolled in the Monmouth College and Monmouth University graduate Electronic Engineering programs. The holdings are bound print documents that were submitted in partial fulfillment of requirements for the Master of Science degree.

Dates

Creation: 1972

Creator

Golubov, Joseph N. (Joseph Nathan) (Author, Person)
Hohmann, Jere W. (Thesis advisor, Person)

Conditions Governing Access

All analog collection holdings are limited to library use only.

Researchers seeking to photocopy collection materials must complete an Application to Photocopy Form.

In some cases, photocopying of collection materials may be performed by the Monmouth University Library staff.

The Monmouth University Library reserves the right to limit or refuse duplication requests subject to the condition of collection materials and/or restrictions imposed by the collection creators or by the United States Copyright Act.

Permission to examine, or copy, collection materials does not imply permission to publish or quote. It is the responsibility of the researcher to obtain such permissions from both the copyright holder and Monmouth University.

Extent

2 Items (print book) : 117 pages ; 8.5 x 11.0 inches (28 cm).

Language of Materials

English

Additional Description

Abstract

This thesis develops different types of circuits which can be implemented to provide a method to detect and correct errors in digital data on a T1 type communication line. The characteristics of the T1 communication line and the signal sent on the line are described. Errors in the transmitted signal can occur on this line and the types and sources of these errors are discussed. The following are described and discussed in detail:

1) The technique of error detection and correction using row and column parity
2) The circuit realization which performs row and column parity error detection and correction.
3) The technique of error detection and correction using cyclic coding.
4) The circuit realization to perform error detection and correction using cyclic coding.

A tabulation is provided which gives numerical results for; probability of having an incorrect frame; bit rate efficiency; probability of having an undetected error; and cost of circuit implmentations in terms of number and type of devices required for the various circuits. For example, by increasing the number of check bits for row end column parity in varying amounts the probability of having an incorrect frame can be varied from 1.833 x 10⁻⁸ to 0.144 x 10⁻⁸. The cost of implmentation is also reduced from 1750 gate leads to 475 gate leads. The tradeoff is in the bit rate efficiency which drops from 84.7% to 43.7%. Similar trends are obtained from the results of cyclic coding circuits.

A comparison of cyclic coding circuits and row and column parity circuits shows that for the same probability of having an incorrect frame the cyclic circuit has a higher bit rate efficiency than the parity circuit by 10% to 11%. The cyclic circuit also requires less elements to implement. However, the parity circuit exhibits a lesser probability of having an undetected error than the cyclic result.

The results provide a criteria for when to use the cyclic coding circuit and when to use the parity circuit. If the data is of a type which does not have to be as error free as possible, then the cyclic decoder is best suited. If the data must be purged of as many errors as possible, then the row and column parity is best suited for its superior ability to detect any uncorrected errors.

Partial Contents

1. Introduction -- 2. Description of errors -- 3. Characteristics of the T1 line -- 4. Error detection and correction using parity checking -- 5. Description of row and column parity check circuit -- 6. Error detection and correction using cyclic coding -- 7. Description of the cyclic coding circuit -- 8. Circuit comparisons -- 9. Conclusions -- Bibliography -- Appendix A. Probability calculations -- Appendix B. Program for probability calculations -- Appendix C. Row and column parity for n=96 bite per word -- Appendix D. Cyclic coding circuit for n=96 bits per word.