Data flow between a central processor and a peripheral device, 1972

Item — Call Number: MU Thesis Bar

Identifier: b2088645

Staff Only

Scope and Contents

From the Collection:

The collection consists of theses written by students enrolled in the Monmouth College and Monmouth University graduate Electronic Engineering programs. The holdings are bound print documents that were submitted in partial fulfillment of requirements for the Master of Science degree.

Dates

Creation: 1972

Creator

Bard, Arnold D. (1944-2017) (Author, Person)
Hohmann, Jere W. (Thesis advisor, Person)

Conditions Governing Access

All analog collection holdings are limited to library use only.

Researchers seeking to photocopy collection materials must complete an Application to Photocopy Form.

In some cases, photocopying of collection materials may be performed by the Monmouth University Library staff.

The Monmouth University Library reserves the right to limit or refuse duplication requests subject to the condition of collection materials and/or restrictions imposed by the collection creators or by the United States Copyright Act.

Permission to examine, or copy, collection materials does not imply permission to publish or quote. It is the responsibility of the researcher to obtain such permissions from both the copyright holder and Monmouth University.

Extent

1 Items (print book) : 57 pages ; 8.5 x 11.0 inches (28 cm).

Language of Materials

English

Additional Description

Abstract

A substantial portion of the typical digital computer is concerned with the transfer of data between the central processor and a variety of peripheral equipment. The intent of this project is to design and build the circuitry required for a particular interface, that is, between a Honeywell DDP-24 central processor and an Uptime punch card. A design for this combination is not known to exist and would be of value.

This project concerns a specific computer and a specific peripheral device; however, the critical elements for control and data flow between any high speed processor and any relatively slow, partially mechanical peripheral devices have a great deal in common. The following list represents the major topics which must be understood and the principal design problems.

1. Internal timing of a central processor.
2. Internal timing of a punch card and synchronization to the central processor.
3. Interrupt and general I/O design of the central processor.
4. Detailed familiarization with currently available bipolar integrated circuits which will be used in the design.
5. Level shifting - The two equipments use different circuit designs which make the logic voltage levels incompatible. This substantially complicates the design.